The present invention mainly relates to flip-flop circuits constituted by transistors formed as semiconductor integrated circuits (LSIs).
Performances required of recent LSIs have been rapidly enhanced in recent years, and LSI manufacturers have competed to achieve higher functionality and higher operation speed. LSI circuits for use in synchronous digital signal processing, for example, are designed to use flip-flop circuits as necessary components. Therefore, to achieve faster LSI circuits, every manufacturer has to increase the speed of flip-flop circuits.
In view of this, various configurations of flip-flop circuits for high speed operation have been proposed to date. For example, a circuit configuration including a bypass circuit for allowing an input signal to be output without change in addition to a master latch and a slave latch is known (see, for example, U.S. Pat. No. 5,656,962 (FIG. 5)).
More specifically, the flip-flop circuit includes: a master portion 205 including a master latch; a slave portion 206 including a slave latch; and a bypass 207, as shown in FIG. 5 of this patent.
The master portion 205 includes a pass gate 310, an inverter 311 and an inverter 312. The master portion 205 holds data input from a data input terminal 209 in synchronization with a clock signal input from a clock signal input terminal while the clock signal is at an H (high) level.
The slave portion 206 holds data output from the master portion 205 and allows the data to be output via an inverter 315 and a pass gate 519 while the clock signal is at an L (low) level.
The bypass 207 includes an inverter 316 and a pass gate 317. The bypass 207 outputs data held in the master portion 205 while the clock signal is at the H (high) level.
That is, in the period after the clock signal has risen and before the clock signal falls, the pass gate 317 of the bypass 207 allows data to pass through. On the other hand, in the period after the clock signal has fallen and before the clock signal rises, the pass gate 519 of the slave portion 206 allows data to pass through and to be output from a data output terminal 208. In this manner, at the rising edge of the clock signal, data from the master portion 205 is output via the bypass 207, which operates faster than the slave portion 206, thereby enabling the data to be output from the data output terminal 208 in a short time.
In the conventional flip-flop circuit, however, physical characteristics at the input and output terminal(s) 208 and/or 209 (i.e., an input capacitance with respect to the data input terminal 209 and/or an output driving capability with respect to the data output terminal 208) vary depending on the state of the clock signal. Therefore, the flip-flop circuit has a drawback in which it is difficult to design and develop a circuit including such a flip-flop circuit in a short period.
Specifically, the input capacitance at the data input terminal 209 is described as follows. When the clock signal is “1” (e.g., at the H level), the pass gate 310 at the input of the master portion 205 is closed. Accordingly, the input capacitance at the data input terminal 209 is equal to the source capacitance of the pass gate 310. On the other hand, when the clock signal is “0” (e.g., at the L level), the pass gate 310 is open. Accordingly, the input capacitance at the data input terminal 209 is equal to the sum of the source and drain capacitances of the pass gate 310, the gate capacitance of the inverter 311, the gate capacitance of the inverter 316 and the drain capacitance of the inverter 312, i.e., is different from that when the clock signal is “1”.
The driving capability at the data output terminal 208 is described as follows. When the clock signal is “0”, the inverter 315 of the slave portion 206 drives a subsequent circuit connected to the data output terminal 208 (via the pass gate 519). On the other hand, when the clock signal is “1”, the inverter 316 of the bypass 207 drives the subsequent circuit (via the pass gate 317) with a driving capability different from that when the clock signal is “0”.
In recent LSI markets, rapid development of LSI circuits and introduction thereof to the markets by using techniques allowing short-term development are much more required than before. To achieve the short-term development of LSI circuits, a circuit design technique using physical-characteristic-extracted data at a logic gate level (i.e., at the level of a circuit such as a flip-flop circuit) is generally more advantageous than a circuit design technique using physical-characteristic-extracted data at a transistor level. Specifically, standard cells corresponding to logic gates such as a flip-flop, a NAND, an inverter and an AND are registered in a library. Then, a cell-base design combining these standard cells is applied to design an LSI circuit, thus enabling the LSI circuit to be designed in a short period.
However, in the case where physical characteristics at the input and output vary depending on the state of a clock signal as described above, it is difficult to extract physical characteristics that are to be registered in a library as those of standard cells. If physical characteristics associated with the respective states of the clock signal are extracted and registered in the library, different operations are needed for the respective states of the clock signal during a timing verification of a circuit using such cells, so that processing becomes very complicated. Therefore, a circuit design using the cell-base design as described above is difficult in reality. In these circumstances, it has been impossible to design and develop circuits including flip-flop circuits in short periods.